Interrupts
..............................................................................................................

The 80C51 provides 5 interrupt sources. These are shown in the table. The External Interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was  transition-activated. If the interrupt was level-activated, then the external requesting source is what controls the request flag, rather than the on-chip hardware.
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers (except see Timer 0 in Mode 3). When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to.
The Serial Port Interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine will  normally have to determine whether it was RI or TI that generated the interrupt, and the bit will have to be cleared in software.
All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be canceled in software. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE
IE also contains a global disable bit, EA, which disables all interrupts at once.
Interrupt
Flag
Vector Address
Reset
-
0000
External 0
IE0
0003h
Timer 0
TF0
000Bh
External 1
IE1
0013h
Timer 1
TF1
001Bh
Serial
RI/TI
0023h
Bit
Symbol
Function
IE.7
EA
Disables all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
IE.6
-
Reserved.
IE.5
-
Reserved.
IE.4
ES
Enables or disables the Serial Port interrupt. If ES=0, the Serial Port interrupt is disabled
IE.3
ET1
Enables or disables the Timer 1 Overflow interrupt. If ET1=0, the Timer 1 interrupt is disabled.
IE.2
EX1
Enables or disables External Interrupt 1. If EX1=0, External interrupt 1 is disabled.
IE.1
ET0
Enables or disables the Timer 0 Overflow interrupt. If ET0=0, the Timer 0 interrupt is disabled.
IE.0
EX0
Enables or disables External Interrupt 0. If EX0=0, External interrupt 0 is disabled.
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